In a semiconductor device, cost reduction is achieved by increasing integration and reducing a chip size. For this purpose, miniaturization of a memory element and a transistor in the semiconductor device has been preceded.
With the miniaturization of the memory element and the transistor, a power supply voltage applied to the semiconductor device also needs to be lowered from the view of reliability. On the other hand, in order to maintain compatibility with existing products as product specifications of the semiconductor device, the power supply voltage supplied to the semiconductor device may be maintained to the same voltage as that in the existing products. For example, when the power supply voltage of 1.8V is externally supplied and an internal power supply voltage in the semiconductor device is 1.5V, the external power supply voltage of 1.8V needs to be reduced to the internal supply voltage of 1.5V.
FIG. 1 is a block diagram showing a configuration of a conventional semiconductor device disclosed in Patent Literature 1. The semiconductor device includes a reference voltage circuit 201, a voltage reducing circuit 202, and an internal circuit 203. The reference voltage circuit 201 outputs a reference voltage VREF to the voltage reducing circuit 202 based on an external power supply voltage VDD. The voltage reducing circuit 202 reduces the external power supply voltage VDD to the internal power supply voltage VDL based on the reference voltage VREF and outputs it to the internal circuit 203.
FIG. 2 shows a configuration of a conventional voltage reducing circuit disclosed in Patent Literature 2. Here, the conventional voltage reducing circuit corresponds to the voltage reducing circuit 202 described above.
The conventional voltage reducing circuit includes an internal power supply section 20 and a current control section 110. The internal power supply section 20 includes a differential circuit section 21 and a voltage supplying section 22. The differential circuit section 21 includes P-type MOSFET (which will be referred to as a “PMOS transistor”, hereinafter) MP12 and MP13 and N-type MOSFET (which will be referred to as “NMOS transistors”, hereinafter) MN12 and MN13.
The PMOS transistor MP12 has a source connected with a first external power supply voltage VDD and a drain connected with a first node N1. The PMOS transistor MP13 has a source connected with the first external power supply voltage VDD, a gate connected with a gate of the PMOS transistor MP12 and a drain. The NMOS transistor MN12 has a drain connected with the first node N1, a source connected with a second node N2, and a gate to which the reference voltage VREF is supplied so as to set an internal power supply voltage VDL. The NMOS transistor MN13 has a drain connected with a drain of the PMOS transistor MP13, a source connected with the second node N2, and a gate connected with a fourth node N4. The first node N1 is used as an output of the differential circuit section 21, and an output voltage VPG is outputted from the first node N1.
The voltage supplying section 22 includes a PMOS transistor MP14 and resistance elements R12 and R13. The PMOS transistor MP14 has a source connected with the first external power supply voltage VDD, a drain connected with a third node N3, and a gate connected with the first node N1, and supplied with the output voltage VPG from the differential circuit section 21. The resistance element R12 is connected between the third node N3 and the fourth node N4. The resistance element R13 is connected between the fourth node N4 and a second external power supply voltage (ground voltage) GND. The third node N3 is used as the output of the voltage supplying section 22, and the internal power supply voltage VDL is outputted from the third node N3.
When the voltage supplying section 22 does not include the resistance elements R12 and R13, the third node N3 is connected to the gate of the NMOS transistor MN13 in place of the fourth node N4.
The current control section 110 includes a PMOS transistor MP11, a resistance element R11, and NMOS transistors MN11 and MN14. The PMOS transistor MP11 has a source connected with the first external power supply voltage VDD and a gate connected with the second power supply voltage GND. The NMOS transistor MN11 has a source connected with the second power supply voltage GND. The resistance element R11 is connected between a drain of the PMOS transistor MP11 and a drain of the NMOS transistor MN11. The NMOS transistor MN14 is a constant current source and has a drain connected with the second node N2 of the differential circuit section 21, a source connected with the second power supply voltage GND, and a gate connected with a gate and the drain of the NMOS transistor MN11.
Next, an operation of the conventional voltage reducing circuit will be described.
The internal power supply voltage VDL can be set based on the reference voltage VREF and a division voltage VMON. The reference voltage VREF serves as an input of the differential circuit section 21, and is supplied to the gate of the NMOS transistor MN12 of the differential circuit section 21 as described above. The division voltage VMON is a voltage supplied from the fourth node N4 when the internal power supply voltage VDL is divided by use of the resistance elements R12 and R13. That is, the division voltage VMON is supplied to the gate of the NMOS transistor MN13 of the differential circuit section 21. In this case, the division voltage VMON is expressed as follows:VMON=VDL×R13/(R12+R13)
In the differential circuit section 21, the division voltage VMON is made stable in the same voltage as the reference voltage VREF, and thus relation between the reference voltage VREF and the division voltage VMON is expressed as:
VREF=VMON=VDL×R13/(R12+R13). Developing this, the internal power supply voltage VDL is expressed as:VDL=VREF×(R12+R13)/R13.
When the external power supply voltage VDD is 1.8V and the internal power supply voltage VDL is 1.5V, it could be understood from the above equation that it is sufficient that the reference voltage VREF is set to be 0.75V and resistance values of the resistance elements R12 and R13 are equal to each other.
A configuration could be considered that the resistance elements R12 and R13 are not arranged and the internal power supply voltage VDL is directly connected to the gate of the NMOS transistor MN 13. In such a case, VREF=VDL.
FIG. 3 is a diagram showing a time-voltage characteristic in an operation of the conventional voltage reducing circuit. In FIG. 3, a horizontal axis shows time and a vertical axis shows voltage.
When the reference voltage VREF is set to be 0.75V after the external power supply voltage VDD is supplied, a current flows through a path from the power supply voltage VDD to the PMOS transistor MP11, the resistance element R11 and the NMOS transistor MN11 in the current control section 110, and a voltage VNG supplied to a gate of the NMOS transistor MN11 increases. As a result, the NMOS transistor MN14 is turned on so that the differential circuit section 21 is activated, which increases the internal power supply voltage VDL from the power supply voltage GND.
At this time, the division voltage VMON also increases with the increase in the internal power supply voltage VDL. When the internal power supply voltage VDL has increased to 1.5V, the division voltage VMON is set to be 0.75V, in which case the reference voltage VREF is equal to the division voltage VMON, so that the internal power supply voltage VDL is consequently controlled at 1.5V.